1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a non-volatile semiconductor memory built therein, and more particularly, to a method of manufacturing a semiconductor device composed of transistors of a single drain structure and transistors of a double drain structure such as a lightly doped drain structure or a graded junction structure.
2. Description of Related Art
Conventionally, in a semiconductor device such as a single chip microcomputer, circuits for a random access memory (RAM) and a read only memory (ROM) are mounted on the same chip in addition to logic circuits. In this case, at least a part of the ROM is formed of a non-volatile memory such as an electrically programmable ROM (EPROM). In the semiconductor device with such a non-volatile memory built therein, at least three types of metal-oxide-semiconductor field effect transistors (MOSFETs), i.e., MOSFETs for a logic circuit, MOSFETs for memory cells (including a MOSFET with a double gate electrode structure), and MOSFETs for input protection are required. Of these MOSFETs, the MOSFETs for the logic circuit preferably include source and drain regions formed so as to have double drain structure such as LDD structure or graded junction structure adapted to withstand hot electrons because the MOSFETs need to have resistance against hot electrons. The MOSFETs for the memory cell have source and drain regions formed so as to have single drain structure because hot electrons need to be effectively generated for writing data in the non-volatile memory cell. Further, in the MOSFETs for input protection, source and drain regions are formed so as to have single drain structure of low resistivity because the MOSFET can be prevented from being destroyed thermally by input electrostatic charge.
Next, a method of manufacturing the above-mentioned conventional semiconductor device will be described below with reference to FIGS. 1A to 1E.
First, as shown in FIG. 1A, a p-type silicon substrate 111 is provided with a memory cell formed region 102a, a MOSFET formed region 102b for input protection, and a MOSFET formed region 102c for a logic circuit on the surface region. In the memory cell formed region 102a, a double gate electrode structure 113a composed of a floating gate electrode 115a, an insulating film 114, and a control gate electrode 115b, is formed on the substrate 111 via a gate insulating film 112. In the MOSFET formed regions 102b and 102c, gate electrodes 113b and 113c of single gate structure are formed on the substrate 111 via the gate insulating films 112. Note that insulating films and regions for isolating elements are not shown because they are well known to a person skilled in the art. Thereafter, phosphorus (P) ions are injected into the substrate 111 with acceleration energy of 100 KeV and a dose amount of 2 to 3.times.10.sup.13 cm.sup.-2 in self-alignment with the double gate structure 113a and gate electrodes 113b and 113c using them as a mask to form n-type low dose amount diffusion layers 116.
Next, as shown in FIG. 1B, a photoresist layer 119 is formed on the whole surface of the substrate 111 and then the photoresist layer 119 is removed from the memory cell formed region 102a using a first photoresist mask. As a result, the MOSFET formed regions 102b and 102c remain covered by the photoresist layer 119. Subsequently, arsenic (As) ions are injected into the substrate 111 with acceleration energy of 70 KeV and a dose amount of 5.0.times.10.sup.15 cm.sup.-2 in self-alignment with the double gate structure 113a using it as a mask. As a result, n-type high dose amount diffusion layers 118 are formed. The n-type diffusion layers 118 functions as source and drain regions of a MOSFET for a memory cell having single drain structure.
Next, as shown in FIG. 1C, the photoresist layer 119 is removed and a silicon oxide film is deposited on the whole substrate 111 by a low pressure CVD method. The silicon oxide film is etched back by an anisotropic plasma etching method, so that side wall insulating films 120a, 120b and 120c are formed on the side walls of the double gate structure 113a and gate electrodes 113b and 113c.
Next, as shown in FIG. 1D, a photoresist layer 121 is formed on the whole surface of the substrate 111. Then, the photoresist layer 121 is removed from the MOSFET formed region 102c for the logic circuit using a second photoresist mask, so that the memory cell formed region 102a and MOSFET formed region 102b for input protection remain covered with the photoresist layer 121. Subsequently, arsenic (As) ions are injected into the substrate 111 with acceleration energy of 70 KeV and dose amount of 3.0.times.10.sup.15 cm.sup.-2 in self-alignment with the gate electrode 113c and side wall insulating film 120c using them as a mask. As a result, n-type high dose amount diffusion layers 122 are formed while the low concentration n-type diffusion layers 116 remain. As a result, the source and drain regions having double drain structure, such as the graded junction structure or LDD structure are completed for the MOSFET for the logic circuit.
Finally, as shown in FIG. 1E, a photoresist layer 123 is formed on the whole surface of the substrate 111. Then, the photoresist layer 123 is removed from the MOSFET formed region 102b for input protection using a third photoresist mask, so that the memory cell formed region 102a and MOSFET formed region 102c for the logic circuit remain covered with the photoresist layer 123. Subsequently, phosphorus (P) ions are injected into the substrate 111 with acceleration energy of 70 KeV and dose amount of 1.0.times.10.sup.15 cm.sup.-2 in self-alignment with the gate electrode 113b and side wall insulating film 120b using them as a mask. As a result, n-type diffusion layers 124 of high dose amount are formed while the low concentration n-type diffusion layers 116 remain. A thermal treatment is performed after the ion injection. In this case, since the phosphorus ion has a greater diffusion coefficient than that of the arsenic ion, phosphorus ions diffuse from the n-type high dose amount diffusion layer to a portion under the side wall insulating film 120b so that the source and drain regions 124 having single drain structure are completed.
As described above, in the conventional method of manufacturing a semiconductor device with a non-volatile memory built therein, the MOSFET having a single drain structure for the memory cell and input protection and the MOSFET having the double drain structure for the logic circuit are formed through a process of injecting impurity into all the MOSFET in common with a low dose amount, and a process of individually injecting impurity into each of the MOSFETs with a high dose amount. Therefore, three photoresist masking processes and four ion injecting processes are required. As a result, it is difficult to reduce manufacturing cost of the semiconductor device, and production yield also is reduced.